(a) Field of the Invention
The present invention relates to a thin film transistor array panel with improved connection to test lines.
(b) Description of Related Art
Recently, flat panel displays such as organic light emitting diode (“OLED”) displays, plasma display panels (“PDPs”), and liquid crystal displays (“LCDs”) have been receiving much attention as possible replacements for the heavy and large cathode ray tubes (“CRTs”).
The PDPs are devices which display characters or images using plasma generated by gas-discharge. The OLED displays are devices which display characters or images by applying an electric field to specific light-emitting organics or high molecule materials. The LCDs are devices which display images by applying an electric field to a liquid crystal layer disposed between two panels and regulating the strength of the electric field to adjust the transmittance of light passing through the liquid crystal layer.
Among the flat panel displays, the LCD and the OLED display each includes a lower panel provided with pixels including switching elements and display signal lines, an upper panel provided with color filters, and a plurality of circuitry elements.
When the display signal lines are disconnected in the process of manufacturing the display device, the disconnection is detected via predetermined tests. Such tests include an array test, a visual inspection (VI) test, a gross test, a module test, and so on.
The array test is used to detect the disconnection of the display signal lines by applying predetermined voltages and sensing whether output voltages are generated or not before a mother glass is divided into separate cells. The VI test is used to detect the disconnection of the display signal lines by applying predetermined voltages to view the panels after the mother glass is divided into separate cells. The gross test is used to determine the image quality and connection status of the display signal lines by applying predetermined voltages to view display states of a screen before mounting driving circuits thereon. Typically, the predetermined voltages are applied after combining the lower panel and the upper panel. The module test is used to determine the optimum operation of the driving circuits after mounting the driving circuits thereon.
The display signal lines are divided into several groups to be tested in the array test and the VI test, and the gross test and the module test are performed in a condition similar to real operation circumstances. For the array test and the VI test, a test line is connected to each group. An end portion of the test line has a large area, which is called a pad, and a test signal is applied to the pad. In this case, the display signal lines and the test line are connected using a conductive layer disposed in a layer different from the display signal lines and the test lines.
However, poor contact occurs among the display signal lines, the test lines and the conductive layer. The poor contact may be caused by etching with an etchant in the process of manufacturing, thereby disconnecting the signal lines from the conductive layer. A method of achieving a better contact between the signal lines and the test line is desired.